A simple CPU has a system clock, a logic control unit, an arithmetic logic unit, an Instruction Counter, an Instruction Register, an Address Register, and an Accumulator.
==== CPU (schema) ====
=System Clock
=Arithmetic Logic Unit
-Arithmetic
-Comparisons
-Boolean Algebra
=Special Purpose Registers
-Instruction Counter (IC)
-Instruction Register (IR)
-Address Register (ADDR)
-Accumulator (ACC)
=General Purpose Registers
-R0
-R1
-R2
-R3
=System Support, Not on CPU Chip
=PROM BIOS
=CMOS
-Date, Time
-Configuration
Description
Component Abbreviation Function
-System Clock CLK The system clock initiates timing signals used to coordinate the actions of different components of the computer.
-Logic Control Unit The logic control unit contains the electronics that decodes instructions, performs the non-arithmetic actions, and sends control signals to other parts of the computer.
-Arithmetic Logic Unit ALU The arithmetic logic unit contains the electronics that performs the functions of arithmetic, comparison, and Boolean operations.
-Instruction Counter or Instruction Pointer IC or IP Tells which memory location to fetch the next instruction from.
-Instruction Register IR Holds the operation code of an instruction while it is being decoded and executed.
-Address Register ADDR Holds the argument field of an instruction while an instruction is being decoded and executed.
-Accumulator ACC Accumulates results of arithmetic and Boolean operations.
==== Anatomy of a Simple CPU Instruction ====
Operation Code Argument Field
Instruction: Tells the computer what to do. Tells the computer where to get data from, store data to, or which instruction to fetch next.
Directive: Tells translator or loader what to do. Specifies options and actions that take place prior to the program being executed.
=Instruction Fetch and Decode Cycles:
-Fetch the next instruction from the memory location identified in the Instruction Counter (IC).
-Load the operation code of the instruction into the Instruction Register (IR).
-Load the Argument Field into the Address Register.
-Automatically increment the Instruction counter by one.
=Execute and Store Cycles:
-Perform the action of the instruction.
==== Directive ====
A directive selects options that affect translation of a program, or that tell system software what to do with the program while it is being translated or being loaded for execution. Classification of an action as directive or instruction is language-dependent. Computer Science majors learn more details about directives when studying compilers and assemblers. The term "pragma" is used with Ada to specify compiler options.
-ORG N Begin loading the code module at memory location N.
-ENTRY N Begin execution at memory location N. The Instruction Counter (IC) is initialized to the number N before the first instruction is executed.
-EQU X Initialize this memory location with the value X when the program is loaded into memory, before the program execution is started. The argument X is called a "literal".
-RES N Reserve N words of memory for data, beginning with this location. This causes N locations to be skipped when the program is being loaded. Whatever was in those locations before loading the program is still there.
==== Memory and Registers ====
Memory locations in a computer are numbered. The lowest memory location is location 0. The computer references each location in memory by a number. That number is called an address. The bit pattern stored in memory at that location is called the contents of that location. The order of numbering bits in a computer word, and of storing words in memory, is done by the design engineer.
Registers often have more bits than main memory. This accommodates additional precision during a sequence of computations. Main memory usually does not have any ability to do anything with data except hold it and transfer it. Registers also have special logic that main memory does not have. For example, it is common to be able to increment registers, do bit manipulation in registers, and other activities.
The first sketch below shows the accumulator with Least Significant Bit (LSB) as bit 0, and the Most Significant Bit (MSB) as bit 15. Conceptually bend the register into a circle to make it a ring. With this is the mental model, you can rotate bits through the register. For example, to rotate bits right 2 places, old bit 0 goes to new position 14; old bit 1 goes to new position 15; old bit 1 goes to new position 1; and so forth.
(missing)
In the example below, the 4-digit hexadecimal numbers represent data and a short program loaded into memory before the program is executed. The blank locations could contain 4-digit hexadecimal number. The Instruction Counter is initialized to the entry point of the program prior to the beginning of execution.
==== Sample Program in Hexadecimal ====
Memory Location Contents in Hex.
00
01
02 0009
03 0005
04
05
06 0602
07 0E03
08 0904
09 1F00
10
CPU
System Clock
Special Purpose Register Contents in Hex
Instruction Counter 0006
Instruction Register
Address Register
Accumulator
The contents of memory location 02 is 0009. In binary, the contents is 0000000000001001.
The contents of memory location 03 is 0005. In binary, the contents is 0000000000000101.
The contents of memory location 06 is 0602. In binary, the contents is 0000011000000010.
The contents of memory location 07 is 0E03. In binary, the contents is 0000111000000011.
The contents of memory location 08 is 0904. In binary, the contents is 0000100100000100.
The contents of memory location 09 is 1F00. In binary, the contents is 0001111100000000.
The contents of other memory locations are arbitrary before execution begins.
The contents of the Instruction Counter is 0006. In binary, the contents is 0000000000000110.
The only thing the memory knows about are the ones and zeros. The machine does not know about hexadecimal, and it does not care. We record the contents in hexadecimal to make it easier for us.
Below is a trace of the execution of the program listed above.
Fetch phase:
The Instruction Counter value is shown in the Fetch column is its value at the beginning of the clock cycle.
The accumulator is shown at the beginning of the fetch phase.
Execute phase:
The Instruction Counter in the Execute phase contains the value at the beginning of the execution phase.
The accumulator is shown at the completion of the execution phase.
Instruction Phase Fetch Execute Fetch Execute Fetch Execute Fetch Execute
Time 0 0 1 1 2 2 3 3
Instruction
Counter 0006 0007 0007 0008 0008 0009 0009 000A
Instruction
Register 06 06 0E 0E 09 09 1F 1F
Address
Register 02 02 03 03 04 04 00 00
Accumulator
garbage 0009 0009 000E 000E 000E 000E 000E
Memory Location 02 0009 0009 0009 0009 0009 0009 0009 0009
Memory Location 03 0005 0005 0005 0005 0005 0005 0005 0005
Memory Location 04 garbage garbage garbage garbage garbage 000E 000E 000E
*** The Instruction Counter is initialized to 0006 by specification of the Entry point prior to the program starting.
In the Execute phase at time 1, the contents of memory location 03 is added to the contents of the Accumulator. What occurs is the addition of the decimal numbers 9 + 5 = 14, which is 0009 + 0005 = 000E in hexadecimal.
====Instructions of our Simple CPU ====
Real computers have many instructions. Simple real computers have about 100 instructions. Main frame computers may have on the order of 200 to 300 instructions. The type and number of instructions are designed into a CPU to give achieve goals of performance and cost.
The Simple CPU for class use was constructed to have only 32 instructions. The Simple Computer has 256 memory locations numbered 0 through 255. The memory is word-addressable, 16 bits per word.
Limiting the instruction set to 32 instructions imposes severe limitations on the efficiency of the computer. I wanted to illustrate basic input and output, load and store, simple arithmetic, simple register operations, simple conditional instructions, simple addressing and indirect addressing. There may be better combinations of instructions that will yield a more efficient system. I invite suggestions for use next semester, subject to the constraint of only 32 instructions. After trying this instruction set on a few examples, better instruction mixes should become apparent.
Operation Code Argument Field Op Code (hex) Action
NOP 00 Perform NO Operation, but do not stop the computer. Example: NOP.
JMP X 01 Jump. Load the contents of the Address Register into the Instruction Counter (IC). Example: JMP 7.
JMP* Rn 02 Jump Indirect. Load the contents of Register n into the Instruction Counter (IC). Example: JMP R3.
CL 03 Clear (set to zero) the Accumulator. Example: CL.
CL Rn 04 Clear (set to zero) Register number n, where n can be 0, 1, 2, or 3. Example: CL R2.
LD# X 05 Load Immediate. Load the Accumulator with the value in the Argument field. Example: LD# 13. This places the number 13 into the accumulator.
LD X 06 Load the contents of memory location X into the accumulator. Example: LD 3.
LD Rn 07 Load the contents of Register number n into the accumulator, where n can be 0, 1, 2, or 3. Example: LD R2.
LD* Rn 08 Load Indirect Rn: Load into the accumulator the contents of the memory location whose address is contained in Register number n, where n can be 0, 1, 2, or 3. Example: LD* R2.
ST X 09 Store the contents of the accumulator into memory location X. Example: ST 2.
ST Rn 0A Store the contents of the accumulator into Register number n, where n can be 0, 1, 2, or 3. Example: ST R2.
ST* Rn 0B Store Indirect Rn: Store the contents of the accumulator into the memory location whose address is contained in Register number n, where n can be 0, 1, 2, or 3. Example: ST* R2.
IN 0C Input a byte from the standard input device into the accumulator. Example: IN.
OUT 0D Output a byte to the standard output device from the accumulator. Example: OUT.
ADD X 0E Add the contents of memory location X to the accumulator, leaving the answer in the accumulator. Example: ADD 4.
ADD Rn 0F Add the contents of Register number n to the accumulator, leaving the answer in the accumulator. The number n can be 0, 1, 2, or 3. Example: ADD R2.
ADD* Rn 10 ADD Indirect. Add to the accumulator the contents of the memory location whose address is contained in Register number n, leaving the answer in the accumulator. The number n can be 0, 1, 2, or 3. Example: ADD* R2.
INC 11 Increment the contents of the accumulator by 1. Example: INC
INC Rn 12 Increment the contents of Register number n by 1. The number n can be 0, 1, 2, or 3. "Increment" means increase the value. Example: INC R2.
DEC Rn 13 Decrement the contents of Register number n by 1. The number n can be 0, 1, 2, or 3. "Decrement" means decrease the value. Example: DEC R2.
AND Rn 14 Boolean (logical) AND the Accumulator with the contents of Register n, where n can be 0, 1, 2, or 3. Leave the answer in the accumulator. Example: AND R2.
OR Rn 15 Boolean (logical) OR the Accumulator with the contents of Register n, where n can be 0, 1, 2, or 3. Leave the answer in the accumulator. Example: OR R2.
NOT 16 Boolean NOT (logical complement) the Accumulator, leaving the answer in the accumulator. Example: NOT.
NOT Rn 17 Boolean NOT (logical complement) the the contents of Register n, where n can be 0, 1, 2, or 3. Leave the answer in Register n. Example: NOT R2.
SBR K 18 Shift the Accumulator Right by K bits, where K can be 0 through 15. Bits shifted out of the accumulator are lost. Vacated bits are set to zero. Example: SBR 3.
SBL K 19 Shift the Accumulator Left by K bits, where K can be 0 through 15. Bits shifted out of the accumulator are lost. Vacated bits are set to zero. Example: SBL 5.
RBL K 1A Rotate the Accumulator Left by K bits, where K can be 0 through 15. Imagine the accumulator as a closed ring. The most significant bit shifts out and into the least significant bit position. Example: RBL 4.
TLSB 1B Test the Least Significant Bit of the Accumulator. Example: TLSB.
if the outcome of the test is false (LSB=0), then go to the next instruction.
If the outcome of the test is true (LSB=1), then skip the next instruction. To do this, increment the Instruction Counter by one (1).
TNE0 1C Test the Accumulator to see if it is Not Equal to zero. Example: TNE0.
If the outcome of the test is false (Accumulator is Equal to zero), then go to the next instruction.
If the outcome of the test is true (Accumulator is not equal to zero), then skip the next instruction. To do this, increment the Instruction Counter by one (1).
TNE0 Rn 1D Test Register number n to see if it is Not Equal to zero, where n can be 0, 1, 2, or 3. Example: TNE0 R2.
If the outcome of the test is false (Rn is Equal to zero), then go to the next instruction.
If the outcome of the test is true (Rn is not equal to zero), then skip the next instruction. To do this, increment the Instruction Counter by one (1).
TLT0 1E Test the Accumulator to see if it is less than to zero. Example: TLT0.
If the outcome of the test is false (Accumulator is Greater Than or Equal to Zero), then go to the next instruction.
If the outcome of the test is true (Accumulator is Less Than zero), then skip the next instruction. To do this, increment the Instruction Counter by one (1).
HLT 1F Halt. Stop the computer. Example: HLT.
Subtraction is implemented by forming the two's complement by performing NOT, followed by INC. Shifting and bit testing instructions are needed to implement multiplication.
Thoughtful assignment of machine codes to instructions would group families of instructions according to specific simple bit patterns. Attention to this detail has not been given for this draft.
==== Sample Program in Using Mnemonics and Symbolic Addresses ====
A symbolic address identifies a location in memory by using symbols rather than numbers. When a symbol is used on the left side of an instruction, the symbol is defined as the number of the associated memory location. In the below program, the symbolic address P is defined as memory location 02. Symbolic address Q is defined as memory location 03. Symbolic address Answer is defined as memory location 04. When a symbolic address is used on the right side of an instruction, the number associated with that symbolic address is substituted.
ORG tells the loader where to begin loading the program into memory.
ENTRY tells the computer where to begin execution after code is in memory. It accomplishes this by placing the argument into the Instruction Counter before execution begins.
Pragma Direction Argument
ORG 02
ENTRY Start
Symbolic
Location Symbolic
Operation
Code Symbolic
Argument
Field Memory Location Contents in Hex.
00 garbage
01 garbage
P EQU 9 02 0009
Q EQU 5 03 0005
Answer RES 2 04 garbage
05 garbage
Start LD P 06 0602
ADD Q 07 0E03
ST Answer 08 0904
HLT 09 1F00
10 garbage
CPU
System Clock
Special Purpose Register Contents in Hex
Instruction Counter 0006
Instruction Register
Address Register
Accumulator
==== Tracing Execution ====
Compared to the earlier trace, this one records entries using symbolic codes, symbolic addresses, and decimal numbers. The first trace example more closely reflects what the computer actually does.
Instruction Phase Fetch Execute Fetch Execute Fetch Execute Fetch Execute
Time 0 0 1 1 2 2 3 3
Instruction
Counter 6 7 7 8 8 9 9 10
Instruction
Register LD LD ADD ADD ST ST HLT HLT
Address
Register P P Q Q Answer Answer 0 0
Accumulator
garbage 9 9 14 14 14 14 14
Memory Location 02 = P 9 9 9 9 9 9 9 9
Memory Location 03 = Q 5 5 5 5 5 5 5 5
Memory Location 04 = Answer garbage garbage garbage garbage garbage 14 14 14
